The present invention relates to a semiconductor device having a plurality of single crystal semiconductor layers each containing at least one of silicon (Si) and germanium (Ge), and carbon (C) as essential constituent elements and a method of manufacturing the same. The semiconductor device of the invention concerns a technique which is effectively applied to high frequency amplifying semiconductor devices and integrated circuits used in wireless communication apparatus and, further, a technique it is useful for use in broad forbidden band semiconductor devices for wireless communication in quasi-milliwave to milliwave regions.
Along with rapid popularization of mobile communication terminals and internet communication in recent yearn, wireless communication capacity has been increased rapidly year by year. Accordingly, necessary band width in the wireless communication has been extended and increase for the demand of communication apparatus intended for usual consumers is expected necessarily in higher frequency bands, that is, from quasi-milliwave to milliwave regions. Semiconductor devices used for electronic circuits in the frequency band described above are predominantly those using compound semiconductor materials represented by GaAs. Recently, SI carbide (hereinafter simply referred to as SIC) having broader forbidden width and more preferred electron transportation characteristics compared with GaAs has been investigated since it is applicable to higher power density at high frequency waves.
Existent methods of forming single crystal semiconductor layers containing Si, Ge, and C, were reported, for example, in Japanese Patent No. 2798576 (Paragraph 10, FIG. 1). In the manufacturing method of the prior art example, a gaseous starting material containing Si atoms, a gaseous starting material containing C atoms and a gaseous starting material containing Ge atoms are used. Further, such gaseous starting materials am thermally decomposed and grown into an Si epitaxial layer containing C and Ge at a vacuum degree of 10$−2 Torr or less capable of neglecting the gas phase reaction. Further, the prior art example shows that a substrate having, on its surface, at least an Si layer and a mask pattern formed on the Si layer is disposed in a gas phase growing vessel, and a gaseous starting material containing Si atoms, a gaseous starting material containing C atoms and a gaseous starting material containing Ge atoms are applied simultaneously to the surface of the substrate at a vacuum degree capable of neglecting the gas phase reaction to selectively grow the Si layer containing C and Ge only at the region on the substrate where the Si layer is exposed.
Further, an example of a method of forming a single crystal layer comprising Si, Ge, and C by using a single starting material gas is described in Applied Physics Letters, Vol. 65, pp 2960, 1994. A polycrystal layer with a Ge compositional ratio of 13% and a C compositional ration of 50% is grown by using tetrakis germane (Ge(Si(CH3)3)4) as the starting material gas.
Further, an existent example of a semiconductor device using a single crystal semiconductor layer containing Si, Ge, and C is also described in JP-A No. 9-283533 (Paragraph 25, FIG. 6). FIG. 19 shows the cross-sectional structure of a bipolar transistor of this example. A high concentration n-Si region 102 is grown on a p-Si substrate 101, an n-Si layer 103 is formed thereon as a collector region, on which a p-SiGe layer 104 as a base region and an n-SiGeC mixed crystal 105 as a an emitter region are grown. Each of the junction boundaries for the collector, the base and the emitter is formed by, e.g., the UHV/CVD process or the like so that relocation is not caused. As the starting gas for effecting epitaxial growth, an organic silane such as silane, disilane, or methyl silane, or an organic germane such as methyl germane and, optionally, ethylene is used. As the doping gas, arsenic or phosphorus is used as an n-impurity and boron or the like is used for a p-impurity.
Since SiC has a high melting point, it is extremely difficult to prepare a large diameter substrate by the pulling-up method as for the Si substrate. Accordingly, a method of forming a substrate by sublimation of a starting material is used. However, even use of the method still involves a drawback that a substrate having high crystal quality and a large area cannot be obtained.
Further, in a semiconductor integrated circuit for use in communication, not all of the circuits handle signals in a high frequency region since integrated circuits requiring information processing of a large capacity in a low frequency region are also necessary. For the integrated circuits, it is optimal to use existent Si semiconductor integrated circuits. Accordingly, a desirable integrated circuit is a combination of an SIC semiconductor device and an Si semiconductor device described above. In this case, while individual semiconductor chips can be mounted in one module, it is more preferred to manufacture born of the semiconductor devices on one and the same substrate. In order to attain the structure, it is necessary to form an SiC layer on an Si substrate.
Further, in the existent semiconductor device using the single crystal semiconductor layer containing Si, Ge, and C described above, the amount of C contained is small and it is of a diamond structure not a blende structure. The solid solubility of C in Si or SiGe mixed crystal as the diamond structure is several % or less, which involves a drawback that the crystallinity is worsened as the C compositional ratio is increased.
The manufacturing methods reported generally so far include the general drawbacks concerning the crystallinity as described above as well as the following drawbacks in fabricating the semiconductor device. In the semiconductor device using SiC for the active layer, it is difficult to dope SiC to a high concentration p-type, which involves drawbacks that a base resistance of a bipolar transistor cannot be formed, and that manufacture of a short channel device which is essential to the high-speed operation of a field effect transistor is difficult.
Further, the drawback in the field effect semiconductor device is that high-speed operation characteristics to be expected inherently for the SiC semiconductor cannot be achieved since the quality of the gate insulating film formed on the SiC surface is poor.